XC2S30-5TQG144C Xilinx Inc.

Part Number:
XC2S30-5TQG144C
Custom Part #:
HS100143
Manufacturer:
Xilinx Inc.
Category:
Integrated Circuits (ICs)
Price:
$ 0
RoHS:
RoHS
Description:
XC2S30-5TQG144C The Spartan-II family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs.
Datasheet:
XC2S30-5TQG144C Datasheet
Authorized Distributor:
EOLSEMI Worldway Electronics
XC2S30-5TQG144C Xilinx Inc. Photos
  • XC2S30-5TQG144C Xilinx Inc.
XC2S30-5TQG144C Xilinx Inc. Description
The Spartan®-II Field-Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The six-member family offers densities ranging from 15,000 to 200,000 system gates, as shown in Table 1. System performance is supported up to 200 MHz. Features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The Spartan-II family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).
XC2S30-5TQG144C Xilinx Inc. Specifications
Features
• Second generation ASIC replacement technology
- Densities as high as 5,292 logic cells with up to
200,000 system gates
- Streamlined features based on Virtex® FPGA
architecture
- Unlimited reprogrammability
- Very low cost
- Cost-effective 0.18 micron process
• System level features
- SelectRAM™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K bit block RAM
· Fast interfaces to external RAM
- Fully PCI compliant
- Low-power segmented routing architecture
- Full readback ability for verification/observability
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution
nets
- IEEE 1149.1 compatible boundary scan logic
• Versatile I/O and packaging
- Pb-free package options
- Low-cost packages available in all densities
- Family footprint compatibility in common packages
- 16 high-performance interface standards
- Hot swap Compact PCI friendly
- Zero hold time simplifies system timing
• Core logic powered at 2.5V and I/Os powered at 1.5V,
2.5V, or 3.3V
• Fully supported by powerful Xilinx® ISE® development
system
- Fully automatic mapping, placement, and routing