XC5VTX150T-2FFG1759I Xilinx Inc.

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Xilinx Inc.
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XC5VTX150T-2FFG1759I the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family.
XC5VTX150T-2FFG1759I Datasheet
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EOLSEMI Worldway Electronics
XC5VTX150T-2FFG1759I Xilinx Inc. Photos
  • XC5VTX150T-2FFG1759I Xilinx Inc.
  • XC5VTX150T-2FFG1759I Xilinx Inc.
  • XC5VTX150T-2FFG1759I Xilinx Inc.
XC5VTX150T-2FFG1759I Xilinx Inc. Description
Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability.
XC5VTX150T-2FFG1759I Xilinx Inc. Specifications
Virtex-5 FPGA Logic
• On average, one to two speed grade improvement over
Virtex-4 devices
• Cascadable 32-bit variable shift registers or 64-bit
distributed memory capability
• Superior routing architecture with enhanced diagonal
routing supports block-to-block connectivity with
minimal hops
• Up to 330,000 logic cells including:
− Up to 207,360 internal fabric flip-flops with clock enable
− Up to 207,360 real 6-input look-up tables (LUTs) with
greater than 13 million total LUT bits
− Two outputs for dual 5-LUT mode gives enhanced
− Logic expanding multiplexers and I/O registers
550 MHz Clock Technology
• Up to six Clock Management Tiles (CMTs)
− Each CMT contains two DCMs and one PLL—up to
eighteen total clock generators
− Flexible DCM-to-PLL or PLL-to-DCM cascade
− Precision clock deskew and phase shift
− Flexible frequency synthesis
− Multiple operating modes to ease performance trade-off
− Improved maximum input/output frequency
− Fine-grained phase shifting resolution
− Input jitter filtering
− Low-power operation
− Wide phase shift range
• Differential clock tree structure for optimized low-jitter
clocking and precise duty cycle
• 32 global clock networks
• Regional, I/O, and local clocks in addition to global
SelectIO Technology
• Up to 1,200 user I/Os
• Wide selection of I/O standards from 1.2V to 3.3V
• Extremely high-performance
− Up to 800 Mb/s HSTL and SSTL
(on all single-ended I/Os)
− Up to 1.25 Gb/s LVDS (on all differential I/O pairs)
• True differential termination on-chip
• Same edge capture at input and output I/Os
• Extensive memory interface support
550 MHz Integrated Block Memory
• Up to 16.4 Mbits of integrated block memory
• 36-Kbit blocks with optional dual 18-Kbit mode
• True dual-port RAM cells
• Independent port width selection (x1 to x72)
− Up to x36 total per port for true dual port operation
− Up to x72 total per port for simple dual port operation
(one Read port and one Write port)
− Memory bits plus parity/sideband memory support for
x9, x18, x36, and x72 widths
− Configurations from 32K x 1 to 512 x 72
(8K x 4 to 512 x 72 for FIFO operation)
• Multirate FIFO support logic
− Full and Empty flag with fully programmable Almost Full
and Almost Empty flags
• Synchronous FIFO support without Flag uncertainty
• Optional pipeline stages for higher performance
• Byte-write capability
• Dedicated cascade routing to form 64K x 1 memory
without using FPGA routing
• Integrated optional ECC for high-reliability memory
• Special reduced-power design for 18 Kbit (and below)
550 MHz DSP48E Slices
• 25 x 18 two’s complement multiplication
• Optional pipeline stages for enhanced performance
• Optional 48-bit accumulator for multiply accumulate
(MACC) operation with optional accumulator cascade
to 96-bits
• Integrated adder for complex-multiply or multiply-add
• Optional bitwise logical operation modes
• Independent C registers per slice
• Fully cascadable in a DSP column without external
routing resources <br />